With a marked price reduction of color plasma display panels (hereafter abbreviated as “PDP”) in recent years, the cost reduction of incorporated semiconductor products has been demanded. For a scan drivers IC for color PDPs, an integrated circuit wherein high voltage lateral IGBTs and low voltage circuits are integrated in a chip are often adopted on a SOI (silicon on insulator) substrate.
In order to reduce the costs of the above-described IC, it is effective to reduce the size of the lateral IGBT that occupies a large area in a chip. For this reason, the current capability of the lateral IGBT at forward bias must be improved. The current capability of the lateral IGBT is measured on at least on-state voltage and characteristics of destroying devices, such as SOA (safe operating area) and ESD (electrostatic discharge).
FIG. 9 shows a general lateral IGBT on a SOI substrate.
An N-type semiconductor layer 3 is bonded on a supporting substrate 1 via a buried insulating film 2. On the surface of the N-type semiconductor layer 3, a P-type base region 4 and an N-type buffer region 8 are formed. On the surface of the P-type base region 4, an N+-type emitter region 5 and a P+-type base contact diffusion region 10 are diffused. On the surface of the N-type buffer region 8, a P+-type collector region 9 is diffused. On the P-type base region 4, a gate electrode 7 extends above a field oxide film 11 via a gate insulating film 6. On the N+-type emitter region 5 and the P+-type base contact diffusion region 10, an emitter electrode 12 is formed, and on the P+-type collector region 9, a collector electrode 13 is formed.
The factors that determine on-state voltage and SOA will be described.
On-state voltage chiefly depends on the resistance component when the device is in the on-state. The channel resistance formed below the gate insulating film 6 is one of major resistance components, and the reduction thereof is important. Whereas, the control of latch up is important for SOA.
As shown in FIG. 10, since a parasitic NPN transistor composed of the N+-type emitter region 5, the P-type base region 4, and the N-type semiconductor layer 3 is present, the equivalent circuit of the lateral IGBT has a thyristor structure as shown in FIG. 11. Once this thyristor causes latch-up, the thyristor cannot be controlled by gate voltage and a low-impedance state is produced bringing in breakdown. The condition of generating latch up is:α(NPN)+α(PNP)≧1where α(NPN) and α(PNP) are the common base current gains of the parasitic NPN transistor and PNP transistor, respectively. Thereby, to control latch-up, it is also important to lower the current gain a of both bipolar transistors.
Since the PNP transistor relates to on-state voltage, the excessive lowering of the current gain α reduces priority to the MOS transistor. Therefore, to prevent latch-up, the action of the parasitic NPN transistor (turn-on) is suppressed. The common base current gain α of the parasitic NPN bipolar transistor is given by the following formula:α=[1−(DE/DP)(NB/NE)(W/LE)]·[1−W2/2LB2]where DE is the diffusion coefficient of minority carriers in the emitter region, DP is the diffusion coefficient of minority carriers in the base region, NB is the impurity concentration in the base region, NE is the impurity concentration in the emitter region, W is the width of the base region, LE is the diffusion length of minority carriers in the emitter region, and LB is the diffusion length of minority carriers in the base region. In order to lower α value obviously, it is effective to increase NB, reduce NE, and increase W.
To suppress the turn-on of the parasitic NPN transistor, it is effective to reduce the base resistance Rb below the emitter region. When the lateral IGBT is in the on state and the collector current is increased, the voltage drop increases in the base resistance Rb. When the voltage drop exceeds the built-in potential Vbi, turn-on is started. Therefore, the reduction of the base resistance Rb is particularly important.
Normally in the device structure of a lateral IGBT, as shown in FIG. 9, a P+-type base contact diffusion region 10 of a high concentration is inserted under the N+-type emitter region 5. Alternatively, a dedicated high-concentration diffusion layer having larger diffusion depth may be diffused from the surface instead of the P+-type base contact diffusion region 10. In any case of the P+-type base contact diffusion region 10 and the dedicated high-concentration diffusion layer, since channel resistance is increased when diffusion reaches under the gate electrode 7, a sufficient margin is required in the distance L1 to the gate electrode 7 shown in FIG. 10. The base resistance becomes the serial resistance of the distance L1 of a low concentration and the distance L2 of a high concentration.
Therefore, the turn-on of the parasitic NPN transistor depends on the voltage drop in the distance L1 having a higher resistance. The distance L1 is easily varied by the widths of the gate electrode 7 and the P+-type base contact diffusion region 10, and their misalignment. In addition, the lateral spread of diffusion is easily influenced by variation of heat treatment (drive-in temperature and time) then it's variation changes the distance L1.
To reduce such variation factors, a device structure wherein a high-concentration region is formed in the entire area under the emitter region has been proposed.
In the invention described in Japanese Patent Application Laid-Open No. 10-242456, as shown in FIG. 12, a high-concentration P-type region 14 is continuously added under a P-type base region 4. In the invention described in Japanese Patent Application Laid-Open No. 2002-270844, as shown in FIG. 13, a high-concentration P-type region 14 is formed under an emitter region 5. The high-concentration P-type region 14 is formed by self-aligning to the gate electrode 7 so as not to affect the channel portion.
In both of the above-described conventional techniques, since on-state voltage depends on the channel resistance of the P-type base region 4, and latch-up depends on the high-concentration P-type region 14. Thereby, the on-state voltage and the latch-up can be independently controlled. Furthermore, since the high-concentration P-type region 14 does not reach the channel region, the variation of channel resistance can be reduced.